Apparatus for radio telecommunication system and method of building up output power

ABSTRACT

A polar loop based radio telecommunication apparatus which has a phase control loop for controlling the phase of a carrier outputted from an oscillator for transmitter, and an amplitude control loop for controlling the amplitude of a transmission output signal outputted from a power amplifier circuit, wherein precharge means is provided on a forward path from a current source, through the power amplifier circuit, to a detection circuit, forming the amplitude control loop, for rapidly increasing a control voltage for the power amplifier circuit to a power threshold upon starting transmission.

CROSS-REFERENCE TO RELATED APPLICATION

The present application relates to subject matters described in the U.S.patent applications being file based on the United Kingdom PatentApplications No. 0212725.6 filed on May 31, 2002, No. 0212729.8 filed onMay 21, 2002, No. 0212723.1 filed on May 21, 2002, No. 0212735.5 filedon May 31, 2002, and No. 0212732.2 filed on May 31, 2002. All of thoseU.S. applications are assigned to the same assignees of the presentapplication.

BACKGROUND OF THE INVENTION

The present invention relates to techniques for improving thecontrollability of output power by a power control signal of a highfrequency power amplifier circuit and for building up without fail theoutput power of the high frequency power amplifier circuit uponstarting, and more particularly, to techniques suitable for applicationin a semiconductor integrated circuit for communication which contains aphase detection circuit and an amplitude detection circuit, and anapparatus for radio telecommunication system such as a portabletelephone which incorporates the semiconductor integrated circuit forcommunication.

One of conventional schemes for radio telecommunication apparatus(mobile telecommunication apparatus) such as a portable telephone is GSM(Global System for Mobile Communication) which is employed in Europe.This GSM scheme uses a phase modulation mode called GMSK (GaussianMinimum Shift Keying) which shifts the phase of a carrier in accordancewith transmission data.

Generally, a high frequency power amplifier circuit is incorporated in atransmission output unit in a radio telecommunication apparatus. Aconventional GSM-based radio telecommunication apparatus employs aconfiguration for controlling a bias voltage of a high frequency poweramplifier circuit to provide output power required for a call by meansof a control voltage outputted from a circuit, called an APC (AutomaticPower Control) circuit, which generates a control signal for atransmission output based on a signal from a detector for detecting atransmission output and a level required for transmission from abaseband LSI.

In recent portable telephones, an EDGE (Enhanced Data Rates for GMSEvolution) scheme has been proposed. The EDGE scheme has dual-modecommunication functions, and relies on GMSK modulation to perform audiosignal communications and on 3π/8 rotating 8-PSK (Phase Shift Keying)modulation to perform data communication. The 8-PSK modulation is suchmodulation that adds an extra amplitude shift to a phase shift of acarrier in the GMSK modulation. Since the 8-PSK modulation can send3-bit information per symbol, in contrast with the GMSK modulation whichsends 1-bit information per symbol, the EDGE scheme can achievecommunications at a higher transmission rate as compared with the GSMscheme.

As one implementation of a modulation mode for imparting information ona phase component and an amplitude component, respectively, of atransmission signal, there is a conventionally known method called“polar loop” which involves separating a signal intended fortransmission into a phase component and an amplitude component,subsequently applying feedback to the separated components through aphase control loop and an amplitude control loop, and combining theresulting components by an amplifier for outputting the combinedcomponents (for example, “High Linearity RF Amplifier Design” byKenington, Peter B., p 162, published by ARTECH HOUSE, INC. in 1979).

A GSM-based communication system is only required to output a phasemodulated signal in accordance with a required output level, so that ahigh frequency power amplifier circuit at a final stage can be operatedin a saturation region, whereas a radio communication system capable ofEDGE-based transmission/reception must perform an amplitude control, sothat a high frequency power amplifier circuit at a final stage must belinearly operated in a non-saturation region. However, with a method ofdriving a high frequency power amplifier circuit used in a conventionalGSM-based communication system, it is difficult to ensure the linearitywhich is required by the high frequency power amplifier circuit in asmall output level region. On the other hand, the polar loopconfiguration can advantageously satisfy the requirement for thelinearity of the high frequency power amplifier circuit, and improve thepower efficiency in the low output level region.

SUMMARY OF THE INVENTION

In this regard, the present inventors considered the employment of thepolar loop configuration in an EDGE-based radio communication system. Asa result, while a prescription is given for portable telephone terminalssupporting EDGE or GSM to increase output power OUT of an output poweramplifier to a power threshold within a fixed time upon startingtransmission, it was found that the polar loop configuration suffersfrom a long time taken until an amplitude control loop is stabilizedupon building up the output power, and resulting difficulties inbuilding up the output power within the prescribed time.

Further, an investigation on the cause of the problems revealed that theamplitude control loop is instable due to a small phase margin and anarrow frequency bandwidth thereof because currently provided outputpower amplifiers do not ensure their operations in a region in which anoutput control voltage is very small.

More specifically, among characteristics required for an output poweramplifier, the control voltage—power characteristic is desired tolinearly increase output power POUT with respect to an output controlvoltage VRAMP, as indicated by a solid line A in FIG. 10. In addition,the output power—gain characteristic is desired to provide a constantgain GPA of the amplifier with respect to the output power OUT, asindicated by a solid line AA in FIG. 11. However, an actual output poweramplifier exhibits the control voltage—power characteristic, asindicated by a broken line B in FIG. 10, in which the output power POUTdoes not linearly change within a range in which the output controlvoltage VRAMP is small, and the output power—gain characteristic, asindicated by a broken line BB in FIG. 11, in which the gain is lowerthan a desired level in the range in which the output control voltageVRAMP is small. As a result, it becomes apparent that if an attempt ismade to build up the output power of the output power amplifier whilethe amplitude control loop is left closed, a long time is taken untilthe amplitude control loop is stabilized, thus making it difficult tobuild up the output power within a prescribed time.

It is an object of the present invention to provide a highly reliableapparatus for radio telecommunication system, such as a portabletelephone that has a function of performing phase modulation andamplitude modulation, which is capable of preventing a long delay instabilizing an amplitude control loop due to a reduction in closed loopfrequency bandwidth caused by a change in the open loop gain. Anadditional drawback is the reduction of phase margin caused by thereduction of open loop gain that may reduce the stability of theamplitude loop.

It is another object of the present invention to provide a highlyreliable apparatus for a radio telecommunication system, such as aportable telephone that has a function of performing phase modulationand amplitude modulation, which is capable of increasing the outputpower of an output power amplifier to a power threshold without failwithin a prescribed time upon starting transmission.

It is another object of the present invention to provide a highlyreliable apparatus for a radio telecommunication system which is capableof increasing the output power of an output power amplifier to a powerthreshold without fail within a prescribed time upon startingtransmission under all conditions of operations.

The aforementioned and other objects and novel features of the presentinvention will become apparent from the description of the specificationand the accompanying drawings.

A representative one of inventions disclosed in the present applicationwill be briefly summarized as follows.

Specifically, a polar loop based radio telecommunication apparatus ofthe present invention has a phase control loop for controlling the phaseof a carrier outputted from an oscillator for transmitter, and anamplitude control loop for controlling the amplitude of a transmissionoutput signal outputted from a power amplifier circuit, wherein theapparatus includes precharge means on a forward path from an amplitudedetection circuit to the power amplifier circuit, forming the amplitudecontrol loop, for rapidly increasing a control voltage for the poweramplifier circuit to a power threshold upon starting transmission. Inthis way, the amplitude loop operates in an open loop way duringprecharge, thus ensuring that the output power of the power amplifiercircuit can be increased to a power threshold within a prescribed timeupon starting transmission.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the general configuration of apolar loop based transmitter circuit according to a first embodiment ofthe present invention, and an exemplary configuration of a radiocommunication system using the same;

FIG. 2 is a block diagram illustrating an exemplary configuration of apolar loop in the transmitter circuit of FIG. 1 in greater detail;

FIG. 3 is a flow chart illustrating a control procedure in the polarloop based transmitter circuit according to the first embodiment of thepresent invention upon building up output power;

FIG. 4 is an explanatory diagram showing a relationship between a changein output level upon building up the output power from the polar loopbased transmitter circuit according to the first embodiment of thepresent invention and a time mask when a required output level,prescribed in the GSM system standard, is low;

FIG. 5 is an explanatory diagram showing a relationship between a changein output level upon building up the output power from the polar loopbased transmitter circuit of the present invention and a time mask whena required output level, prescribed in the GSM system standard, is high;

FIG. 6 is a schematic circuit diagram illustrating an exemplaryconfiguration of a forward path of an amplitude control loop in detail,showing a second embodiment of the present invention;

FIG. 7 is a schematic circuit diagram illustrating an exemplaryconfiguration of a forward path of an amplitude control loop in detail,showing a third embodiment of the present invention;

FIG. 8 is a graph showing a level change in the forward path of theamplitude control loop upon building up the output power in the thirdembodiment;

FIG. 9 is a circuit diagram illustrating an exemplary specific circuitconfiguration of a variable gain amplifier circuit;

FIG. 10 is a characteristic diagram showing a relationship between theoutput power and output control voltage of an output power amplifierthat forms part of a radio communication system which uses the polarloop based transmitter circuit according to another embodiment of thepresent invention;

FIG. 11 is a characteristic diagram showing a relationship between theoutput power and power gain of the output power amplifier that formspart of the radio communication system which uses the polar loop basedtransmitter circuit according to another embodiment of the presentinvention; and

FIGS. 12A and 12B are graphs showing a relationship among an outputcontrol voltage VRAMP and the gains of an output power amplifier and avariable gain amplifier circuit, and a relationship between the outputcontrol voltage VRAMP and the output power of the output power amplifierin the polar loop based transmitter circuit according to anotherembodiment of the present invention.

DESCRIPTION OF THE INVENTION

FIG. 1 illustrates the general configuration a polar loop based radiotelecommunication apparatus according one embodiment of the presentinvention. In FIG. 1, the polar loop based radio telecommunicationapparatus comprises a high frequency IC 100 which is capable ofperforming the GMSK modulation in a GSM system, and the 8-PSK modulationin an EDGE system; a power module 200 which includes a high frequencypower amplifier circuit (hereinafter called the power amplifier) 210 fordriving an antenna ANT for transmission, a coupler 220 for detectingtransmission power, and the like; a baseband circuit 300 for generatingI/Q signals based on transmission data (baseband signal), and generatinga control signal for the high frequency IC 100 and a bias voltage VBIASfor the power amplifier 210 in the power module 200; an oscillator fortransmitter TxVCO for generating a phase modulated transmission signal(carrier); and a loop filter LPF1 for limiting the bandwidth of a phaseloop.

The high frequency IC 100 is implemented as a semiconductor integratedcircuit on a single semiconductor chip. The chip of the high frequencyIC 100 is formed thereon with a reception-related circuit 190 comprisinga low noise amplifier (LNA); a mixer (Rx-MIX) for directlydownconverting a received signal to a baseband signal; a high gainprogrammable gain amplifier (PGA); and the like, in addition totransmission-related circuits, as described below in detail. The highfrequency IC 100, oscillator for transmitter TxVCO, loop filter LPF, andthe like may be mounted on a single insulating substrate such as aceramic substrate to form a module.

The foregoing high frequency IC 100 of the embodiment, which constitutesa polar loop, comprises a phase divider circuit 110 for generating asignal, the phase of which is shifted by 90° from an oscillating signalφIF at an intermediate frequency generated by an oscillator IF-VCO; aquadrature modulation circuit 120 for mixing I/Q signals supplied fromthe baseband LSI 300 with the signal divided by the phase dividercircuit 110 for quadrature modulation; a mixer 131 for mixing a feedbacksignal from the oscillator for transmitter TxVCO with an oscillatingsignal φRF from a high frequency oscillator RF-VCO for downconversion toa signal such as 80 MHz; a phase detection circuit 140 for detecting adifference in phase between an output signal of the mixer 131 and anoutput signal of the quadrature modulation circuit 120; a mixer 132 formixing a detection signal from the coupler 220 for detecting an outputlevel of the power amplifier 210 with the oscillating signal φRF from ahigh frequency oscillator RF-VCO; a feedback variable gain amplifiercircuit MVGA for amplifying an output of the mixer 132; an amplitudedetection circuit 150 for comparing the amplified signal with the outputsignal of the quadrature modulation circuit 120 to detect an amplitudedifference; a loop filter LPF2 for generating a voltage in accordancewith an output of the amplitude detection circuit 150 and for limiting afrequency bandwidth of an amplitude loop; a forward variable gainamplifier circuit IVGA for amplifying an output of the loop filter LFP2;a gain control circuit 160 for controlling the gains of the variablegain amplifier circuit MVGA and IVGA; a register 170 for setting controlinformation, operation mode and the like within the chip; a sequencer180 for outputting a timing signal for each of the circuits within thechip based on values set in the register 170 to operate the circuit in apredetermined order in accordance with an operation mode; and the like.After IVGA, there are a VIC (voltage to current controller), a capacitorC4 and a level shifter LVS, followed by the switch SW1.

In this embodiment, an amplitude loop is formed by the coupler 220—mixer132—variable gain amplifier circuit MVGA—amplitude detection circuit150—loop filter LPF2—variable gain amplifier circuit IVGA—poweramplifier 210. Also, a phase loop is formed by the phase detectioncircuit 140—loop filter LPF1—oscillator for transmitter TxVCO—mixer131—phase detection circuit 140. Specifically, if there is a phasedifference between an output signal of the quadrature modulation circuit120 and a feedback signal from the mixer 131, a voltage for reducing thephase difference is supplied to a frequency control terminal of theoscillator for transmitter TxVCO, such that the phase of the feedbacksignal from the mixer 131 matches the phase of the output signal of thequadrature modulation circuit 120. This phase loop performs such acontrol that prevents the phase of the output of the oscillator fortransmitter TxVCO from shifting due to fluctuations in power supplyvoltage and a change in temperature. The oscillator for transmitterTxVCO has a constant amplitude.

Further, in this embodiment, the output of the variable gain amplifiercircuit MVGA is fed back to the phase detection circuit 140 such that apath comprised of the coupler 220—mixer 132—variable gain amplifiercircuit MVGA can be used as a common feedback path for the amplitudeloop and phase loop.

In the amplitude loop, the output of the power amplifier 210 is detectedby the coupler 220, the detection signal of which is converted to anintermediate frequency bandwidth (IF) by the mixer 132, and amplified bythe variable gain amplifier circuit MVGA to generate a feedback signalSFB which is supplied to the amplitude detection circuit 150. Then, theamplitude detection circuit 150 compares a transmission signal modulatedby the quadrature modulation circuit 120 with the feedback signal SFB todetect an amplitude difference which is then amplified by the variablegain amplifier circuit MVGA, and applied to an output control terminalof the power amplifier 210 as a control voltage VAPC for performing anamplitude control.

In this embodiment, the gains of the variable gain amplifier circuitsMVGA, IVGA are controlled by the gain control circuit 160 in a reversedirection in accordance with a control voltage VRAMP from the basebandLSI 300 such that the sum of their gains is substantially constant. Thiscontrol is performed by the following reason. As the open loop gain mustbe kept constant for maintaining a constant frequency bandwidth for theamplitude loop, when the amplitude loop is used to control the outputpower of the power amplifier 210, a change in the gain of the variablegain amplifier circuit MVGA on the feedback path causes a change in thegain in the amplitude loop, resulting in a reduced bandwidth, a reducedphase margin and a lower stability of the loop.

In this embodiment, for controlling the output power of the poweramplifier 210, when the gain of the variable gain amplifier circuit MVGAon the feedback path is increased, the gain of the variable gainamplifier circuit IVGA on the forward path is reduced on the contrary,and when the gain of the variable gain amplifier circuit MVGA on thefeedback path is reduced, the gain of the variable gain amplifiercircuit IVGA on the forward path is increased on the contrary. In thisway, the open loop gain can be kept constant, so that the frequencybandwidth for the amplitude loop is kept constant as well.

Now, detailed description will be made on a gain control for thevariable gain amplifier circuit IVGA on the forward path and thevariable gain amplifier circuit MVGA on the feedback path.

A portable telephone terminal which supports EDGE or GSM controls apower amplifier to increase or reduce the output power POUT to a desiredvalue within a fixed time. In a polar loop, this power control isperformed by controlling the gain of the variable gain amplifier circuitMVGA. Specifically, since a reduction in the gain of the variable gainamplifier circuit MVGA results in a smaller feedback signal in theamplitude loop, the amplitude loop reacts by increasing the RF gain GPA(POUT/PIN) of the power amplifier, in order to match the feedback signalwith a reference signal SREF from the modulation circuit 120, andconsequently this reaction increases the output power POUT. For reducingthe output power POUT, the gain of the variable gain amplifier circuitMVGA may be increased. In this embodiment, the gain of the variable gainamplifier circuit MVGA is controlled by the control voltage VRAMP fromthe baseband LSI 300. Moreover, the proportion of a reduction or anincrease in the gain GMVGA of the variable gain amplifier circuit MVGAis always equal to the proportion of an increase or a reduction in theRF gain GPA of the power amplifier.

For this control strategy, a change in the gain of the variable gainamplifier circuit MVGA in response to the control voltage VRAMP exhibitsa straight line descending to the right, as indicated by a solid lineGMA in FIG. 12A, while a change in the gain of the power amplifier 210in response to the control voltage VRAMP exhibits a straight lineascending to the right, as indicated by a solid line GPA in FIG. 12A.Also, this causes the output power POUT of the power amplifier 210 tolinearly increase in response to the control voltage VRAMP, as shown inFIG. 12B. The output power POUT of the power amplifier 210 expressed indBm linearly increases with the VRAMP expressed in volts.

On the other hand, the reference signal SREF from the modulation circuit120, which is modulated in conformity to 8-PSK and has a varyingamplitude component, is controlled by the action of the amplitudecontrol loop such that an amplitude component of the output power POUTof the power amplifier 210 matches the reference signal SREF. In thisevent, the output power POUT of the power amplifier 210 is modulated ata desired value by the aforementioned power control. In this way, thepolar loop can modulate the output power of the power amplifier inconformity with 8-PSK. In addition, since the polar loop cansimultaneously support GMSK as well, an operated output power controlfunction (APC function), which has been conventionally provided by anexternally attached IC, is not required anymore.

In addition to the foregoing, this embodiment is configured such thatthe power amplifier 210 can be selectively supplied, at its outputcontrol terminal, with an output voltage of the variable gain amplifiercircuit IVGA or the control voltage VRAMP from the baseband LSI 300through a switch SW1. Specifically, the high frequency power amplifiercircuit 210 is controlled by a control voltage from the amplitude loopin an 8-PSK modulation mode, while in a GMSK modulation mode, the poweramplifier 210 is directly supplied with the control voltage VRAMP fromthe baseband LSI 300, instead of the control voltage from the amplitudeloop, such that the output of the power amplifier 210 can be controlled.The embodiment also allows the amplitude loop to control the poweramplifier when operating in GMSK mode. The switch SW1 can be switched bysetting the register 170 from the baseband LSI 300.

As described above, since the polar loop can correctly control the phaseand amplitude of the output of the power amplifier 210 by a commonaction of the phase loop and amplitude loop, this is suitable for a dualmode transmitter circuit which supports both GMSK and EDGE modulationschemes. This is because GMSK modulation scheme provides transmissioninformation only in a phase component, whereas the EDGE schemeadditionally provides information in an amplitude component forincreasing the data rate. Thus, a transmitter circuit which supportsonly the GMSK scheme conventionally performs such a control thatprovides only a constant amplitude at the output of the power amplifier,so that the conventional transmitter circuit cannot support a schemesuch as EDGE which involves a varying amplitude. Since the polar loopcompares the feedback signal from the output of the power amplifier 210with the output of the modulation circuit 120, the output of the poweramplifier 210 (precisely, average output power of the power amplifier)can be controlled by varying the gain of the variable gain amplifiercircuit as previously described. This is used during power ramping only.

During power ramping, the reference signal is always of constantamplitude. The only way to increase the output power of the poweramplifier is to reduce the gain of the variable gain amplifier MVGA tocontrol power ramping.

During the useful part of the burst, the variable gain amplifier gain ismaintained constant, so that the output power of the power amplifierperfectly replicates the amplitude modulation of the reference signal.So, when the GSMK mode is used, the output power remains constant and,when the EDGE mode is used, the output power varies like as 8-PSKsignal.

In either of the GSM and EDGE schemes, however, the standard prescribesthat the power in a rising (build-up) period, a falling (build-down)period, and a data transmission period must always fall within apredetermined time mask at an antenna end, but it is relativelydifficult to implement a circuit which satisfies the standardparticularly in respect to the rising period. In the following, anembodiment which can satisfy the standard in this respect will bedescribed in greater detail.

FIG. 2 illustrates the configuration of the phase loop and amplitudeloop in greater detail. As illustrated in FIG. 2, an attenuator ATT isprovided between the coupler 220 and mixer 132 for attenuating theoutput of the coupler 220 and supplying the attenuated output to themixer 132, and low pass filters MLPF1, MLPF2 are provided between themixer 132 and variable gain amplifier circuit MVGA and between thevariable gain amplifier circuit MVGA and amplitude detection circuit150, respectively, for removing unwanted harmonics. Also, in thisembodiment, a switch SW0 is provided for selectively inputting theoutput level of the power amplifier 210 detected by the coupler 220 andfed back through the feedback path to the phase detection circuit 140 oramplitude detection circuit 150.

Further, in this embodiment, provided behind the variable gain amplifiercircuit IVGA are a charge pump CGP for charging or discharging dependingon a differential output of the variable gain amplifier circuit IVGA togenerate a voltage in accordance with the output of the variable gainamplifier circuit IVGA, and a level shift circuit LVS for shifting thevoltage generated by the charge pump CGP by approximately 0.6 V in thenegative direction. Additionally, the LVS can be designed to produce thesame gain. The charge pump CGP is comprised of a pair of current sourcesIS1, IS2, and a capacitor C4, and a switch SW11 is provided between thecurrent sources IS1, IS2 and the capacitor C4 for shutting down theloop.

An output node N1 of the charge pump CGP is connected to a prechargecurrent source PCI for precharging this node through a switch SW12.Further provided in this embodiment are a level detection circuit DCTfor comparing a signal from the modulation circuit 120 with a feedbacksignal of the amplitude loop to detect whether or not the feedbacksignal reaches a predetermined level, and a flip-flop FF1 operated by anoutput signal of the level detection circuit DCT to generate an ON/OFFcontrol signal for the switches SW11, SW12. The level detection circuitDCT is configured such that its output signal changes to high level whenthe feedback signal reaches −5.9 dBm. The feedback signal at −5.9 dBmcorresponds to the level of the feedback signal when the output controlterminal (VAPC) of the power module 200 is at a level such as −11 dBm.The shift level circuit LVS is provided because the charge pump CGP isnot capable of providing 0 V due to the nature of the current sourceIS2.

Next, the operation involved in building up the output power in thepolar loop based transmitter circuit according to this embodiment willbe described with reference to a flow chart of FIG. 3.

In the output power build-up operation, the oscillator for transmitterTxVCO is first turned on (step S1). Subsequently, I, Q signals are sentfrom the baseband LSI 300 to the modulation circuit 120 to modulate anintermediate frequency signal φIF and supplies the modulated signal tothe phase detection circuit 140 and amplitude detection circuit 150. Inthis event, the phase detection circuit 140 is fed back with atransmission signal of the oscillator for transmitter TxVCO afterdownconverted by the mixer 131. The phase detection circuit 140 comparesthe phase of the feedback signal with that of the modulated signal tostart such a control that matches the phases of the two signals witheach other (step S2). The amplitude detection circuit 150 is alsoapplied with the modulated signal and a detection signal from thecoupler 220 through the feedback path.

Next, the flip-flop FF1 is reset by a reset signal RS, and the switchSW11 on the forward path of the amplitude loop is turned off by theoutput signal of the flip-flop FF1 to open the loop (step S3). In thisevent, when the variable gain amplifier circuit IVGA is implemented by ageneral differential amplifier circuit as illustrated in FIG. 9, thevariable gain amplifier circuit IVGA is short-circuited between aninverting input terminal and a non-inverting input terminal. This isdone in order to maintain a reference voltage for capacitors C2, C3 anda resistor R3 within the loop filter LPF2 on the amplitude loop and toavoid sudden fluctuations in the output of the variable gain amplifiercircuit IVGA when the amplitude loop is closed.

Also, substantially simultaneously with the loop being opened, theswitch SW12 is turned on to start precharging the capacitor C4 of thecharge pump CGP by the precharge current source PCI (step S4).Subsequently, as the level detection circuit DCT determines that themodulated signal matches in level with the feedback signal from theamplitude loop, the level detection circuit DCT operates the flip-flopFF1 as a latch to change its output (steps S5, S6). This causes theswitch SW12 to turn off to stop precharging, and the switch SW11 on theforward path to turn on to close the amplitude loop, thereby startingthe amplitude control (step S7). Also, at this time, the variable gainamplifier circuit IVGA releases the differential input terminals fromthe short-circuited state.

The foregoing operation is automatically executed by a sequencer 180 bysending a transmission starting command from the baseband LSI 300 to thehigh frequency IC 100. Then, the output control voltage VRAMP is alreadyactive before the switch SW11 is turned on to close the amplitude loopto control the power module 200 to build up its output power to adesired level.

As described above, in this embodiment, as soon as the capacitor C4 inthe amplitude loop is precharged, the output power can be ramped up inthe required time condition, as shown in FIG. 4, thereby making itpossible to build up the output power within a time mask prescribed inthe EDGE scheme (the same applies to the GMSK scheme). FIG. 4 shows atime mask and an associated build-up operation when a required outputlevel is relatively high such as 27 dBm at a location relatively farfrom a base station, while FIG. 5 shows a time mask and an associatedbuild-up operation when a required output level is relatively high suchas 13 dBm at a location relatively far from a base station. When therequired output level is relatively low, the output power can be builtup within the prescribed time mask by delaying the start of precharge bya predetermined time, for example, 10 μsec, as shown in FIG. 5.

FIG. 6 illustrates a second embodiment of a precharge circuit.

The precharge circuit in the second embodiment comprises a timer TMR forcontrolling the precharge current source PCI in addition to the likecircuit in the first embodiment. The timer TMR can be configured tomeasure the time in response to a clock signal supplied from thebaseband LSI 300. Also, the timer TMR may be provided integrally withother timers within the sequencer 180. The timer TMR is startedsimultaneously with the start of precharge at step S4 in FIG. 3, and theprecharge current source PCI is turned off, for example, after the lapseof 5 μsec. In this way, the precharge can be terminated even if nochange is found in the output of the level detection circuit DTC becausethe feedback signal has not reached the predetermined level at thattime.

Even if constants of elements constituting the precharge circuit are setby design such that the output of the level shift circuit LVS, i.e., theoutput control voltage (VAPC) of the power module 200 reaches a levelsuch as −11 dB in about 5 μsec after the start of precharge, variationsdue to manufacturing may cause a build-up rate of the output power to belower than expectancy. Therefore, if the precharge takes a long time, atime significantly longer than 5 μsec, the output power of the powermodule 200 cannot be build up to a power threshold within apredetermined time (28 sec) defined by the time mask. The secondembodiment solves this problem.

In the embodiment of FIG. 6, the precharge current source PCI iscontrolled to be on and off by the timer TMR. Alternatively, an AND gatemay be provided for taking logical AND of the output of the flip-flopFF1 (invertor INV in FIG. 6) and the output of the timer TMR, such thatthe switch SW12 is turned off by the earlier one of these outputs toterminate the precharge. However, it is preferable from a viewpoint oftiming to control on and off the precharge current source PCI using thetimer TMR and to turn off the switch SW12 using the output of theflip-flop FF1 (invertor INV), as is the case with the embodiment of FIG.6.

More specifically, a regulated current source generally presents aslower reaction than the switch SW12, so that if the precharge wereterminated by turning off the precharge current source PCI using theoutput of the flip-flop FF1 when the level detection circuit DTCpresents a change in the output, the output power could fall within aprohibited range of the time mask due to a delay in the reaction of thecurrent source PCI when variations due to manufacturing cause the outputpower to be much higher than expected. Thus, the switch SW12 ispreferably turned off using the output of the flip-flop FF1 (invertorINV) as is done in the foregoing embodiment.

On the other hand, considering that variations due to manufacturingcause the build-up rate of the output power to be lower than expected,when the precharge current source PCI is turned off using the timer TMRin such a case, as is done in the foregoing embodiment, the output powerreached at the end of the precharge period is higher than the outputpower that the amplitude loop would reach by itself due to a delayedreaction of the precharge current source PCI. For this reason, theembodiment configured as such is advantageous in its ability to advance,even slightly, the build-up of the output power.

The embodiments in FIG. 6 and next FIG. 7 show exemplary configurationsof the level detection circuit DTC. The level detection circuit DTC inthese embodiments comprises a first AC-DC converting means comprised ofa diode D1 and a capacitor C11 for converting a signal (for example, anAC signal at 80 MHz) SREF supplied from the modulation circuit 120 fordefining a reference level of −5.9 dBm to a DC signal; a second AC-DCconverting means comprised of a diode D2 and a capacitor C12 forconverting a feedback signal SFB from the feedback path of the amplitudeloop to a DC signal; and a comparator CMP comprised of a differentialamplifier for comparing the converted signals with each other.

FIG. 7 illustrates a third embodiment of the precharge circuit.

The third embodiment applies a two-stage precharge method forprecharging in stages the capacitor C4 which forms part of the chargepump CGP. Specifically, a switch SW13 is provided between a regulatedvoltage source CV1 (0.1 V) which provides a voltage as a reference for ashift amount (−0.6 V on the output side) in the level shift circuit LVS,and the node N1 to which the capacitor C4 is connected, such that theregulated voltage source CV1 can be utilized as a precharge powersupply. In addition, the precharge current source PCI used hereinsupplies a smaller current value than the precharge current sources PCIin the first and second embodiments. Then, in the third embodiment, asillustrated in FIG. 8, the switch SW13 is first turned on within a shorttime T1 immediately after the output power is build up to precharge thecapacitor C4 to 0.1 V by the regulated voltage source CV1. Subsequently,the switch SW12 is turned on to slowly precharge the capacitor C4 toapproximately 0.4 V by the precharge current source PCI over arelatively long time T2.

In the foregoing embodiment, the switch SW12 for precharge control isturned off using the output of the level detection circuit DCT in orderto prevent a delay in timing at which the precharge is terminated.Considering more strictly, there is a detection delay in the leveldetection circuit DCT which detects that the output power of the powermodule 200 reaches −11 dBm, and a delay in the timing at which theswitch SW12 is turned off using the output of the level detectioncircuit DCT indicative of the detection, so that the capacitor C4 islikely to be excessively precharged in the meantime. Therefore, thethird embodiment employs the precharge current source PCI which suppliesa relatively small current value to reduce the precharge rate. Inaddition, before the capacitor C4 is precharged by the precharge currentsource PCI, the capacitor C4 is relatively rapidly precharged up to 0.6V so that the LVS output reaches 0.1 V, utilizing the regulated voltagesource CV1 for shifting, and then is slowly precharged by the prechargecurrent source PCI. In this way, the capacitor C4 can be prevented fromthe excessive precharge.

During the precharge, the variable gain amplifier circuit IVGA isshort-circuited between the inverting input terminal and non-invertinginput terminal, and its output is opened (by SW11 in FIG. 7). Then,simultaneously with the termination of the precharge, the two inputterminals are active, while the output is also active.

While the invention made by the present inventors has been specificallydescribed in connection with several embodiments, it should beunderstood that the present invention is not limited to theaforementioned embodiments but may be modified in various manner withoutdeparting from the spirit and scope of the invention. For example, whilethe third embodiment utilizes the regulated voltage source CV1 forshifting in the level shift circuit LVS for the precharge at the firststage, a separate regulated voltage source may be provided for supplyinga voltage lower than a target precharge level (for example, 0.4 V) forthe amplitude loop to perform the precharge at the first stage. However,an increase in circuit scale can be prevented by utilizing the regulatedvoltage source CV1 for shifting as in the third embodiment.

While the present invention has been described in connection with adual-band system to which the present invention is applied, where thesystem is configured to provide for communications in accordance withtwo schemes, i.e., the GSM 900 scheme and DCS 1800 scheme, the presentinvention can be utilized as well for permitting communications whichinvolves phase modulation in accordance with an 8-PSK modulation mode,in addition to a GMSK modulation mode, in a triple-band system which isconfigured to provide for communications in accordance with either theGSM scheme or DCS scheme, or in accordance with a PCS (PersonalCommunication System) 1900 scheme in addition to these schemes orcommunications using 850 MHz.

It should be further understood by those skilled in the art thatalthough the foregoing description has been made on embodiments of theinvention, the invention is not limited thereto and various changes andmodifications may be made without departing from the spirit of theinvention and the scope of the appended claims.

1.-12. (canceled)
 13. A method of building up output power in a radiotelecommunication apparatus having a phase control loop for controllingthe phase of a carrier outputted from an oscillator for a transmitter,and an amplitude control loop for controlling the amplitude of atransmission output signal outputted from a power amplifier circuit,said method comprising the steps of: starting first said phase controlloop; opening said amplitude control loop after said phase control loopis stabilized to perform a precharge for raising the control signal ofthe power amplifier so that the output power rises up to a powerthreshold; terminating said precharge when said forward path reaches thepower threshold; and closing said amplitude control loop to build up theoutput power of said power amplifier circuit.
 14. An apparatus forcontrolling a power amplifier operating on a carrier signal, theapparatus comprising a feedback path for conveying a sample of theoutput of the power amplifier to comparison means arranged to output anamplitude control signal related to the difference in amplitude of saidsampled amplifier output and a modulation signal to beamplitude-modulated onto the carrier signal, and a forward path forconveying the amplitude control signal to an input of the poweramplifier to control the power amplification, wherein the forward pathincludes control means which operates at start up of the power amplifierunder low power conditions to remove the amplitude control signal fromthe input and apply a ramping voltage to the input to increase the speedwith which the output of the power amplifier reaches a power threshold,at which the ramping voltage is terminated and the amplitude controlsignal is re-applied to the input of the power amplifier.
 15. Anapparatus as claimed in claim 14, in which the forward path includes aloop filter comprising a capacitor, and in which the control meanscomprises a current source which is connected to the capacitor togenerate said ramping voltage.
 16. An apparatus as claimed in claim 14,in which the amplitude control signal is removed from the input of thepower amplifier by tri-stating a device in the forward path.
 17. Anapparatus as claimed in claim 14, in which the forward path includes avariable gain amplifier, and the control means short-circuits the inputsof the variable gain amplifier to retain the reference voltage from thecomparison means when the amplitude control signal is removed from thepower amplifier.
 18. An apparatus as claimed in claim 14, includingdetector means to detect the amplitude peak signals at the inputs of thecomparison means that receive said sampled amplifier output andmodulation signal, respectively, the detector means being adapted toproduce a control signal that disconnects the predetermined voltagesignal from the power amplifier and reconnects the amplitude controlsignal.
 19. An apparatus as claimed in claim 18, in which the detectormeans produces said control signal when the sampled amplifier outputequals or exceeds said modulation signal.
 20. An apparatus as claimed inclaim 14, in which the control means includes a timer that operates toensure that the ramping voltage is terminated and the amplitude controlsignal is re-applied to the power amplifier a predetermined maximum timeafter the ramping voltage is applied to the input.
 21. A mobiletelecommunications terminal incorporating apparatus as claimed in claim14.